Integrated batteryless electron timer

Hiroshi Watanabe*, Tomomi Ushijima, Norio Hagiwara, Chiomi Okada, Takeshi Tanabe


研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)


From the viewpoint of information security, the semiconductor timing devices are reviewed, and a promising cell with floating gate (FG) is proposed as an integrated batteryless electron timer. The first issue is the difficulty in the timing precision, which is related to the trap-detrapping phenomena in the tunnel oxide between the FG and the silicon surface. The basic idea to resolve this issue is to monitor the trap-free cells among a plurality of prepared cells. The integrated batteryless electron timer is composed of a plurality of single-polysilicon-type solid-state aging devices that are connected in parallel. The first sample is fabricated in a standard complementary metal-oxide-semiconductor process, and the measurements clearly exhibit the first evidence that we succeeded to remove the trap-detrapping- related fluctuation in the ticking operation. The resultant secondary issues on the precision, i.e., the manufacturing fluctuation (subjecting to the central-limit theorem) and the temperature dependence, are also briefly discussed.

頁(從 - 到)792-797
期刊IEEE Transactions on Electron Devices
出版狀態Published - 1 三月 2011


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