Instruction set extension exploration in multiple-issue architecture

I. Wei Wu*, Zhi Yuan Chen, Jyh-Jiun Shann, Chung-Ping Chung

*此作品的通信作者

研究成果: Conference contribution同行評審

8 引文 斯高帕斯(Scopus)

摘要

To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized instruction set extension (ISE) or to increase instruction issue width. Previous studies have shown that deploying ISE in multiple-issue architecture can significantly improve performance. However, identifying ISE for multiple-issue architecture by using current ISE exploration algorithms will result in unnecessary waste of silicon area and limitation of performance improvement. This is because most algorithms overlook two important considerations: (1) only packing the operations lying on the critical path into ISE can improve performance; (2) the critical path usually changes after packing operations into an ISE. With these considerations, this paper presents an algorithm for ISE exploration based on list scheduling and Ant Colony Optimization (ACO), in which combines ISE exploration and the critical path identification (i.e. instruction scheduling). Results indicate that our approach outperforms the previous work in both performance improvement and area efficiency.

原文English
主出版物標題Design, Automation and Test in Europe, DATE 2008
頁面764-769
頁數6
DOIs
出版狀態Published - 25 8月 2008
事件Design, Automation and Test in Europe, DATE 2008 - Munich, Germany
持續時間: 10 3月 200814 3月 2008

出版系列

名字Proceedings -Design, Automation and Test in Europe, DATE
ISSN(列印)1530-1591

Conference

ConferenceDesign, Automation and Test in Europe, DATE 2008
國家/地區Germany
城市Munich
期間10/03/0814/03/08

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