Influence of postdeposition annealing on physical and electrical properties of high-k Yb2TiO5 gate dielectrics

Tung Ming Pan*, Li Chen Yen, Chien Hung Chiang, Tien-Sheng Chao

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

The structure and electrical properties of a high-k Yb2TiO 5 gate dielectric deposited on Si(100) substrates through reactive cosputtering were investigated. X-ray diffraction, X-ray photoelectron spectroscopy and atomic force microscopy were used to study the morphological and chemical features of these films as functions of the growth conditions. The Yb2TiO5 dielectrics annealed at 800°C exhibited a thinner capacitance equivalent thickness, a lower gate leakage current, a smaller density of interface state, and a relatively lower hysteresis voltage compared to those at other annealing temperatures. These results are attributed to the formation of a rather well-crystallized Yb2TiO5 structure and composition.

原文English
主出版物標題Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6
主出版物子標題New Materials, Processes, and Equipment
頁面247-252
頁數6
版本1
DOIs
出版狀態Published - 30 12月 2010
事件Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting - Vancouver, BC, Canada
持續時間: 26 4月 201027 4月 2010

出版系列

名字ECS Transactions
號碼1
28
ISSN(列印)1938-5862
ISSN(電子)1938-6737

Conference

ConferenceAdvanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting
國家/地區Canada
城市Vancouver, BC
期間26/04/1027/04/10

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