Integrated sensor interface circuits require power-efficient high-accuracy data converters. In many applications, the best choice is to use incremental A/D converters (IADCs) incorporating extended counting. In this paper, we discuss the operation and design of IADCs, including single-loop and MASH architectures. When using a direct-feed-forward modulator, the IADC accumulates the residue voltage, and it is easily to implement a hybrid scheme of extended counting. Several hybrid schemes are review and discussed. A multi-step extended counting scheme is discussed for high-resolution power-efficient conversion. Optimal trade-off between high order and high oversampling ratio is critical for energy efficiency. A two-step IADC is discussed, which extends the performance of an N th-order IADC close to that of a (2N-1)th-order IADC, with reduced power. An implemented device uses the circuitry of a second-order IADC (IADC2) to achieve a performance close to that of a third-order IADC. The two-step operation can be extended to multi-step one, and the SQNR performance can be increased significantly. The two-step operation can be extended to multi-step operation, which can boost up the order of SQNR and further improve the energy efficiency drastically.
|頁（從 - 到）||612-623|
|期刊||IEEE Journal on Emerging and Selected Topics in Circuits and Systems|
|出版狀態||Published - 1 12月 2015|