Incremental ADC with parallel counting

Tao He, Chia-Hung Chen, Yi Zhang, Gabor C. Temes

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

An incremental ADC (lADC) using parallel counting is proposed to achieve both high accuracy and power efficiency. By operating the IADC and the counting logic alternatively within two clock phases, the proposed scheme finishes a full conversion within fewer conversion cycles. The only additional circuitry for the parallel counting is a single comparator, much less than the add-ons in other multi-step topologies. Also, the parallel counting technique can be implemented with different IADC topologies.

原文English
主出版物標題2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1017-1020
頁數4
ISBN(電子)9781509063895
DOIs
出版狀態Published - 27 9月 2017
事件60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, 美國
持續時間: 6 8月 20179 8月 2017

出版系列

名字Midwest Symposium on Circuits and Systems
2017-August
ISSN(列印)1548-3746

Conference

Conference60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
國家/地區美國
城市Boston
期間6/08/179/08/17

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