TY - GEN
T1 - Incremental ADC with parallel counting
AU - He, Tao
AU - Chen, Chia-Hung
AU - Zhang, Yi
AU - Temes, Gabor C.
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/27
Y1 - 2017/9/27
N2 - An incremental ADC (lADC) using parallel counting is proposed to achieve both high accuracy and power efficiency. By operating the IADC and the counting logic alternatively within two clock phases, the proposed scheme finishes a full conversion within fewer conversion cycles. The only additional circuitry for the parallel counting is a single comparator, much less than the add-ons in other multi-step topologies. Also, the parallel counting technique can be implemented with different IADC topologies.
AB - An incremental ADC (lADC) using parallel counting is proposed to achieve both high accuracy and power efficiency. By operating the IADC and the counting logic alternatively within two clock phases, the proposed scheme finishes a full conversion within fewer conversion cycles. The only additional circuitry for the parallel counting is a single comparator, much less than the add-ons in other multi-step topologies. Also, the parallel counting technique can be implemented with different IADC topologies.
KW - Analog-to-digital converter
KW - Delta sigma modulator
KW - Extended data converters
KW - High resolution
KW - Incremental data converters
KW - Sensor interfaces
KW - Ultra-low-power
UR - http://www.scopus.com/inward/record.url?scp=85034076161&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2017.8053099
DO - 10.1109/MWSCAS.2017.8053099
M3 - Conference contribution
AN - SCOPUS:85034076161
T3 - Midwest Symposium on Circuits and Systems
SP - 1017
EP - 1020
BT - 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
Y2 - 6 August 2017 through 9 August 2017
ER -