Improvements of Fermi-level pinning and NBTI by fluorinated HfO 2-CMOS

Chao Sung Lai, Woei Cherng Wu, Huai Hsien Chiu, Jer Chyi Wang, Pai Chi Chou, Tien-Sheng Chao*

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

Improvement of Fermi-level pinning (FLP) and relaxation of negative-bias-temperature-instability (NBTI) for CMOS without interfacial layers was achieved by fluorine incorporation into HfO2. The driving current capability was increased up to 48% and 45% for n-MOSFET and p-MOSFET, respectively. It's caused by the oxygen vacancy was blocked by the fluorine incorporated interface and resulted in the suppression of the interfacial oxide growth to achieved thinner effective oxide thickness (EOT). The improvement included the Fermi-level pinning shift from ∼0.1eV to ∼0.02eV for samples without and with fluorination, respectively. Vth shifts under NBTI stressing were relaxed from positive 350mv to negative 270mv for control and fluorinated samples, respectively. It is due to the Si-F bondings broken under NBTI stressing which the released-fluorine re-incorporate to passivate the HfO2 bulk.

原文English
主出版物標題2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
DOIs
出版狀態Published - 1 12月 2010
事件2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 - Hong Kong, China
持續時間: 15 12月 201017 12月 2010

出版系列

名字2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

Conference

Conference2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
國家/地區China
城市Hong Kong
期間15/12/1017/12/10

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