A cap oxide layer was employed to substantially decrease nickel residues and passivate the trap states of the devices. F+ implantation was used to drive Ni in α-Si layer to induce crystallization (DIC) process with cap oxide to reduce Ni concentration and minimize the trap-state density. As a result, DIC-TFT with cap oxide exhibit higher field-effect mobility, lower subthreshold slope, lower threshold voltage, higher on/off current ratio, and lower trap-state density (Nt) compared with conventional MIC TFTs.
|主出版物標題||Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6|
|主出版物子標題||New Materials, Processes, and Equipment|
|出版狀態||Published - 30 12月 2010|
|事件||Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting - Vancouver, BC, Canada|
持續時間: 26 4月 2010 → 27 4月 2010
|Conference||Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting|
|期間||26/04/10 → 27/04/10|