Improved output ESD protection by dynamic gate floating design

Hun Hsien Chang, Ming-Dou Ker*

*此作品的通信作者

研究成果: Article同行評審

8 引文 斯高帕斯(Scopus)

摘要

A dynamic gate floating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-μm CMOS process. Index Terms-ESD, ESD protection, output buffer.

原文English
頁(從 - 到)2076-2078
頁數3
期刊IEEE Transactions on Electron Devices
45
發行號9
DOIs
出版狀態Published - 1 12月 1998

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