Improved multi-level control of RRAM using pulse-train programming

Liang Zhao, Hong Yu Chen, Shih Chieh Wu, Zizhen Jiang, Shimeng Yu, Tuo-Hung Hou, H. S.Philip Wong, Yoshio Nishi

    研究成果: Conference contribution同行評審

    11 引文 斯高帕斯(Scopus)

    摘要

    Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.

    原文English
    主出版物標題Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014
    發行者IEEE Computer Society
    頁面1-2
    頁數2
    ISBN(列印)9781479922178
    DOIs
    出版狀態Published - 28 4月 2014
    事件2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014 - Hsinchu, Taiwan
    持續時間: 28 4月 201430 4月 2014

    出版系列

    名字Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014

    Conference

    Conference2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014
    國家/地區Taiwan
    城市Hsinchu
    期間28/04/1430/04/14

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