Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages

Kuan-Neng Chen, C. K. Tsang, A. W. Topol, S. H. Lee, B. K. Furraan, D. L. Rath, J. Q. Lu, A. M. Young, S. Purushothaman, W. Haensch

    研究成果: Paper同行評審

    10 引文 斯高帕斯(Scopus)

    摘要

    In this paper we investigated the effect of Cu bonding quality on inter-level via structural reliability for 3D manufacturing applications. We developed a Cu bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes prove the feasibility of reliable and manufacturable 3D integrated circuits and packages.

    原文English
    頁面195-202
    頁數8
    出版狀態Published - 9月 2006
    事件23rd International VLSI Multilevel Interconnection Conference, VMIC 2006 - Fremont, CA, United States
    持續時間: 26 9月 200628 9月 2006

    Conference

    Conference23rd International VLSI Multilevel Interconnection Conference, VMIC 2006
    國家/地區United States
    城市Fremont, CA
    期間26/09/0628/09/06

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