Improve latch-up immunity by circuit solution

Hui Wen Tsai, Ming-Dou Ker

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS devices through special circuit design can effectively reduce the latchup trigger current that injecting into the core circuit blocks. Therefore, the latchup immunity of I-test with positive or negative trigger current applied at the I/O pins can be significantly improved.

    原文English
    主出版物標題Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
    發行者Institute of Electrical and Electronics Engineers Inc.
    頁面527-530
    頁數4
    ISBN(電子)9781479999286, 9781479999286
    DOIs
    出版狀態Published - 25 8月 2015
    事件22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, Taiwan
    持續時間: 29 6月 20152 7月 2015

    出版系列

    名字Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
    2015-August

    Conference

    Conference22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
    國家/地區Taiwan
    城市Hsinchu
    期間29/06/152/07/15

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