Implementation of pipelined FastICA on FPGA for real-time blind source separation

Kuo Kai Shyu*, Ming Huan Lee, Yu Te Wu, Po Lei Lee

*此作品的通信作者

研究成果: Article同行評審

73 引文 斯高帕斯(Scopus)

摘要

Fast independent component analysis (FastICA) algorithm separates the independent sources from their mixtures by measuring non-Gaussian. FastICA is a common offline method to identify artifact and interference from their mixtures such as electroencephalogram (EEG), magnetoencephalography (MEG), and electrocardiogram (ECG). Therefore, it is valuable to implement FastICA for real-time signal processing. In this paper, the FastICA algorithm is implemented in a field-programmable gate array (FPGA), with the ability of real-time sequential mixed signals processing by the proposed pipelined FastICA architecture. Moreover, in order to increase the numbers precision, the hardware floating-point (FP) arithmetic units had been carried out in the hardware FastICA. In addition, the proposed pipeline FastICA provides the high sampling rate (192 kHz) capability by hand coding the hardware FastICA in hardware description language (HDL). To verify the features of the proposed hardware FastICA, simulations are first performed, then real-time signal processing experimental results are presented using the fabricated platform. Experimental results demonstrate the effectiveness of the presented hardware FastICA as expected.

原文English
頁(從 - 到)958-970
頁數13
期刊IEEE Transactions on Neural Networks
19
發行號6
DOIs
出版狀態Published - 2008

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