Implementation of array structured maximum likelihood decoders.

Kuei-Ann Wen*, Jhing Fa Wang, Jau Yien Lee, Ming Yung Lin

*此作品的通信作者

    研究成果: Conference contribution同行評審

    摘要

    Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay-commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmissions are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.

    原文English
    主出版物標題Proc Int Conf on Systolic Arrays
    發行者Publ by IEEE
    頁面227-236
    頁數10
    ISBN(列印)0818688602
    DOIs
    出版狀態Published - 1 12月 1988

    出版系列

    名字Proc Int Conf on Systolic Arrays

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