Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay-commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmissions are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.