TY - GEN
T1 - Implementation of a hardware-efficient EEG processor for brain monitoring systems
AU - Chen, Chiu Kuo
AU - Chua, Ericson
AU - Tseng, Shao Yen
AU - Fu, Chih Chung
AU - Fang, Wai-Chi
PY - 2010
Y1 - 2010
N2 - This paper presents a complexity-efficient architecture for an EEG signal separation processor incorporating ICA with lossless data compression. An average correlation result of 0.9044 is achieved while transmitted EEG data bandwidth and power consumption are reduced by 41.6%. The chip area, operating frequency, and estimated power consumption of the proposed EEG architecture in UMC 90nm SP-HVT CMOS technology are 1,133 by 1,133 um2, up to 32MHz, and approximately 0.70mW at 0.9V supply voltage and 5 MHz operating frequency, respectively.
AB - This paper presents a complexity-efficient architecture for an EEG signal separation processor incorporating ICA with lossless data compression. An average correlation result of 0.9044 is achieved while transmitted EEG data bandwidth and power consumption are reduced by 41.6%. The chip area, operating frequency, and estimated power consumption of the proposed EEG architecture in UMC 90nm SP-HVT CMOS technology are 1,133 by 1,133 um2, up to 32MHz, and approximately 0.70mW at 0.9V supply voltage and 5 MHz operating frequency, respectively.
UR - http://www.scopus.com/inward/record.url?scp=79960735673&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2010.5784735
DO - 10.1109/SOCC.2010.5784735
M3 - Conference contribution
AN - SCOPUS:79960735673
SN - 9781424466832
T3 - Proceedings - IEEE International SOC Conference, SOCC 2010
SP - 164
EP - 168
BT - Proceedings - IEEE International SOC Conference, SOCC 2010
T2 - 23rd IEEE International SOC Conference, SOCC 2010
Y2 - 27 September 2010 through 29 September 2010
ER -