Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

Po Yi Kuo, Jer Yi Lin, Tien-Sheng Chao

研究成果: Conference contribution同行評審

13 引文 斯高帕斯(Scopus)

摘要

The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (DNW)-length (Lnw) × width (WNW) × thickness (TNW)-to 80nm×13nm×3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) ∼ 61 mV/dec., steep driving swing (D.S.) ∼ 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.

原文English
主出版物標題2015 IEEE International Electron Devices Meeting, IEDM 2015
發行者Institute of Electrical and Electronics Engineers Inc.
頁面6.3.1-6.3.4
ISBN(電子)9781467398930
DOIs
出版狀態Published - 16 2月 2015
事件61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States
持續時間: 7 12月 20159 12月 2015

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2016-February
ISSN(列印)0163-1918

Conference

Conference61st IEEE International Electron Devices Meeting, IEDM 2015
國家/地區United States
城市Washington
期間7/12/159/12/15

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