TY - GEN
T1 - Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing
AU - Kuo, Po Yi
AU - Lin, Jer Yi
AU - Chao, Tien-Sheng
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/2/16
Y1 - 2015/2/16
N2 - The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (DNW)-length (Lnw) × width (WNW) × thickness (TNW)-to 80nm×13nm×3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) ∼ 61 mV/dec., steep driving swing (D.S.) ∼ 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.
AB - The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (DNW)-length (Lnw) × width (WNW) × thickness (TNW)-to 80nm×13nm×3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) ∼ 61 mV/dec., steep driving swing (D.S.) ∼ 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.
UR - http://www.scopus.com/inward/record.url?scp=84963997696&partnerID=8YFLogxK
U2 - 10.1109/IEDM.2015.7409639
DO - 10.1109/IEDM.2015.7409639
M3 - Conference contribution
AN - SCOPUS:84963997696
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 6.3.1-6.3.4
BT - 2015 IEEE International Electron Devices Meeting, IEDM 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 61st IEEE International Electron Devices Meeting, IEDM 2015
Y2 - 7 December 2015 through 9 December 2015
ER -