This paper presents the impacts of an advanced shell doping profile (SDP) on the electrical characteristics of a junctionless (JL) FET in terms of OFF-current, subthreshold swing (SS), and ON-current by a numerical simulator. Due to the potential mirroring effect, a special observation stemming from the SDP, the carriers can enter the intrinsic region from the doped surface reducing the series resistance though the junction depth is smaller than 5 nm. The proposed doping profile provides an additional structure parameter for designing a JL FET showing the mitigated short-channel effects, a better SS, and a higher ON/OFF current ratio for sub-20-nm channel length. Compared with traditional devices, a JL FET with the proposed SDP shows a lower OFF-current by decades and less electrical characteristics variation caused by the nanowire diameter variation. The SDP not only reduces the series resistance of a JL FET but also poses a possible solution of avoiding the negative impacts of quantum confinement for advanced technology nodes.