Impacts of pulse conditions on endurance behavior of ferroelectric thin-film transistor non-volatile memory

In this work, the ferroelectric thin-film transistor (Fe-TFT) with polycrystalline-silicon (poly-Si) channel and HfZrO _x gate dielectric is fabricated to study the characteristics of non-volatile memory (NVM). Significant threshold voltage (V _TH) modulation can be achieved with low pulse voltages less than ±3.5 V and pulse widths within 1 μs. In order to achieve the NVM characteristics of low voltage and high speed operation, the impact of the program/erase (PRG/ERS) pulse voltage (V _PRG/V _ERS) and pulse width on endurance is a critical consideration. In the study of the pulse width effect on endurance, it can be observed that the V _TH in PRG-state exhibits the wake-up effect at both short and long pulse widths. In addition, with the increase of pulse width, the V _TH in the PRG-state exhibits significant fatigue effect and subthreshold swing (SS) degradation effect. For V _TH in the ERS-state, the increase of the pulse width also exhibits the fatigue effect and the SS degradation effect, which is dominated by the SS degradation effect at long pulse widths. In the study of the pulse voltage effect on endurance, the increase of V _PRG shows the imprint effect that the V _TH in either PRG- or ERS-state reveals a decreasing trend. When the V _ERS increases, the SS of the PRG- and ERS-states is degraded, and the fatigue effect of the PRG-state is enhanced. Moreover, the retention characteristics of poly-Si Fe-TFTs exhibit stable characteristics at both room temperature and 50 °C.