Impacts of high-κ offset spacer on 65-nm node SOI devices

Ming Wen Ma*, Tien-Sheng Chao, Kuo Hsing Kao, Jyun Siang Huang, Tan Fu Lei

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.

原文English
主出版物標題2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
頁面697-700
頁數4
出版狀態Published - 5月 2006
事件2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, 美國
持續時間: 7 5月 200611 5月 2006

出版系列

名字2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
1

Conference

Conference2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
國家/地區美國
城市Boston, MA
期間7/05/0611/05/06

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