@inproceedings{47c3574ffdd14fa9a427adbb5958f6bc,
title = "Impacts of high-κ offset spacer on 65-nm node SOI devices",
abstract = "In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.",
keywords = "Fringing electric field, High-κ, Offset spacer dielectric, Silicon-on-insulator (SOI)",
author = "Ma, {Ming Wen} and Tien-Sheng Chao and Kao, {Kuo Hsing} and Huang, {Jyun Siang} and Lei, {Tan Fu}",
year = "2006",
month = may,
language = "English",
isbn = "0976798565",
series = "2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings",
pages = "697--700",
booktitle = "2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings",
note = "2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings ; Conference date: 07-05-2006 Through 11-05-2006",
}