Impact of vpass interference on charge-trapping NAND flash memory devices

Yi Hsuan Hsiao, Hang Ting Lue, Wei Chen Chen, Kuo Pin Chang, Bing-Yue Tsui, Kuang Yeu Hsieh, Chih Yuan Lu

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)


The impact of adjacent word-line's pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference.

頁(從 - 到)136-141
期刊IEEE Transactions on Device and Materials Reliability
出版狀態Published - 1 一月 2015


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