Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

Ming-Dou Ker; Yong Ru Wen; Wen Yi Chen; Chun Yu Lin

doi:10.1109/ISNE.2010.5669188

Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

Ming-Dou Ker^*, Yong Ru Wen, Wen Yi Chen, Chun Yu Lin

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

11 引文斯高帕斯（Scopus）

摘要

Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the im portant factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.

原文	English
主出版物標題	2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
頁面	100-103
頁數	4
DOIs	https://doi.org/10.1109/ISNE.2010.5669188
出版狀態	Published - 1 12月 2010
事件	2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, 台灣持續時間: 18 11月 2010 → 19 11月 2010

出版系列

名字	2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Conference

Conference	2010 International Symposium on Next-Generation Electronics, ISNE 2010
國家/地區	台灣
城市	Kaohsiung
期間	18/11/10 → 19/11/10

存取文件

10.1109/ISNE.2010.5669188

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Link to publication in Scopus

引用此

Ker, M.-D., Wen, Y. R., Chen, W. Y., & Lin, C. Y. (2010). Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. 於 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program (頁 100-103). 文章 5669188 (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program). https://doi.org/10.1109/ISNE.2010.5669188

@inproceedings{3b7469f6d5154035b5f60df997c1b0ae,

title = "Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process",

abstract = "Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the im portant factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.",

keywords = "Electrostatic discharge (ESD), Pickup",

author = "Ming-Dou Ker and Wen, {Yong Ru} and Chen, {Wen Yi} and Lin, {Chun Yu}",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/ISNE.2010.5669188",

language = "English",

isbn = "9781424466948",

series = "2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program",

pages = "100--103",

booktitle = "2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program",

note = "2010 International Symposium on Next-Generation Electronics, ISNE 2010 ; Conference date: 18-11-2010 Through 19-11-2010",

}

Ker, M-D, Wen, YR, Chen, WY & Lin, CY 2010, Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. 於 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program., 5669188, 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program, 頁 100-103, 2010 International Symposium on Next-Generation Electronics, ISNE 2010, Kaohsiung, 台灣, 18/11/10. https://doi.org/10.1109/ISNE.2010.5669188

Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. / Ker, Ming-Dou; Wen, Yong Ru; Chen, Wen Yi 等.
2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program. 2010. p. 100-103 5669188 (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

AU - Ker, Ming-Dou

AU - Wen, Yong Ru

AU - Chen, Wen Yi

AU - Lin, Chun Yu

PY - 2010/12/1

Y1 - 2010/12/1

N2 - Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the im portant factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.

AB - Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the im portant factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.

KW - Electrostatic discharge (ESD)

KW - Pickup

UR - http://www.scopus.com/inward/record.url?scp=78751555467&partnerID=8YFLogxK

U2 - 10.1109/ISNE.2010.5669188

DO - 10.1109/ISNE.2010.5669188

M3 - Conference contribution

AN - SCOPUS:78751555467

SN - 9781424466948

T3 - 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

SP - 100

EP - 103

BT - 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

T2 - 2010 International Symposium on Next-Generation Electronics, ISNE 2010

Y2 - 18 November 2010 through 19 November 2010

ER -

Ker MD, Wen YR, Chen WY, Lin CY. Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. 於 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program. 2010. p. 100-103. 5669188. (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program). doi: 10.1109/ISNE.2010.5669188

Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

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