@inproceedings{6241db4806a546a1b510e65c1648281c,
title = "Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection",
abstract = "Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.",
author = "Liao, {Seian Feng} and Tang, {Kai Neng} and Ming-Dou Ker and Yeh, {Jia Rong} and Chiou, {Hwa Chyi} and Huang, {Yeh Jen} and Tsai, {Chun Chien} and Jou, {Yeh Ning} and Lin, {Geeng Lih}",
year = "2015",
month = oct,
day = "16",
doi = "10.1109/ECCTD.2015.7300108",
language = "English",
series = "2015 European Conference on Circuit Theory and Design, ECCTD 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 European Conference on Circuit Theory and Design, ECCTD 2015",
address = "United States",
note = "European Conference on Circuit Theory and Design, ECCTD 2015 ; Conference date: 24-08-2015 Through 26-08-2015",
}