Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

Seian Feng Liao, Kai Neng Tang, Ming-Dou Ker, Jia Rong Yeh, Hwa Chyi Chiou, Yeh Jen Huang, Chun Chien Tsai, Yeh Ning Jou, Geeng Lih Lin

    研究成果: Conference contribution同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.

    原文English
    主出版物標題2015 European Conference on Circuit Theory and Design, ECCTD 2015
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子)9781479998777
    DOIs
    出版狀態Published - 16 10月 2015
    事件European Conference on Circuit Theory and Design, ECCTD 2015 - Trondheim, Norway
    持續時間: 24 8月 201526 8月 2015

    出版系列

    名字2015 European Conference on Circuit Theory and Design, ECCTD 2015

    Conference

    ConferenceEuropean Conference on Circuit Theory and Design, ECCTD 2015
    國家/地區Norway
    城市Trondheim
    期間24/08/1526/08/15

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