Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology

Jung Sheng Chen*, Ming-Dou Ker

*此作品的通信作者

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.

    原文English
    主出版物標題2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual
    頁面664-665
    頁數2
    DOIs
    出版狀態Published - 2007
    事件45th Annual IEEE International Reliability Physics Symposium 2007, IRPS - Phoenix, AZ, United States
    持續時間: 15 4月 200719 4月 2007

    出版系列

    名字Annual Proceedings - Reliability Physics (Symposium)
    ISSN(列印)0099-9512

    Conference

    Conference45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
    國家/地區United States
    城市Phoenix, AZ
    期間15/04/0719/04/07

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