Impact of channel fin aspect ratio on multi-fin field effect transistors

Silicon-based field effect transistors (FETs) with multiple-channel-fins are promising alternatives for the sub-32-nm complementary metal oxide semiconductor (CMOS) technologies. However, their device characteristics are sensitive to the channel-fin aspect ratio (AR = the fin height / the fin width). In this study, the dependences of device characteristics on various ARs for single- and multi-fin transistors are examined using a full three-dimensional device simulation. The threshold voltage (V_th variation of the triple-fin transistor is smaller than that of the single-fin transistor due to the relatively larger effective device width. The triple-fin transistors with fin-typed FET (FinFET) structure (AR = 2) exhibit rather stable V_th, roll-off characteristics because of the more uniform potential distribution inside the channel. The results of our study show that the driving current, transconductance, gate capacitance, intrinsic gate delay and cutoff frequency of FinFETs are superior to that of tri-gate (AR= 1) and quasi-planar (AR = 0.5) FETs. From the layout viewpoint, the FinFETs shows fascinating layout area efficiency. Consequently, to design a device with the subthreshold swing < 70 mV/dec, the layout area of FinFETs is 1.67 and 1.33 times smaller than those of quasi-planar and tri-gate FETs.