Impact of back gate bias on hot-carrier effects of n-channel Tri-Gate FETs (TGFETs)

Chia Pin Lin*, Bing-Yue Tsui

*此作品的通信作者

    研究成果: Conference contribution同行評審

    7 引文 斯高帕斯(Scopus)

    摘要

    The hot-carrier effects of non-planar tri-gate SOI FET (TGFET) with back-gate bias were investigated. Negative back gate bias could raise the influence of buried oxide defects and then degrade the device quickly. For TGFETs with ultra-narrow fin width and side gate extension, the smaller buried oxide interface area and more obvious screening effect terminate the field lines to obviate the back gate bias efficiently. The extrapolated hot-carrier lifetime encourages the TGFETs as promising sub-10nm devices.

    原文English
    主出版物標題2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
    頁面82-83
    頁數2
    DOIs
    出版狀態Published - 1 12月 2006
    事件2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Hsinchu, Taiwan
    持續時間: 24 4月 200626 4月 2006

    出版系列

    名字International Symposium on VLSI Technology, Systems, and Applications, Proceedings

    Conference

    Conference2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
    國家/地區Taiwan
    城市Hsinchu
    期間24/04/0626/04/06

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