TY - GEN
T1 - Impact of back gate bias on hot-carrier effects of n-channel Tri-Gate FETs (TGFETs)
AU - Lin, Chia Pin
AU - Tsui, Bing-Yue
PY - 2006/12/1
Y1 - 2006/12/1
N2 - The hot-carrier effects of non-planar tri-gate SOI FET (TGFET) with back-gate bias were investigated. Negative back gate bias could raise the influence of buried oxide defects and then degrade the device quickly. For TGFETs with ultra-narrow fin width and side gate extension, the smaller buried oxide interface area and more obvious screening effect terminate the field lines to obviate the back gate bias efficiently. The extrapolated hot-carrier lifetime encourages the TGFETs as promising sub-10nm devices.
AB - The hot-carrier effects of non-planar tri-gate SOI FET (TGFET) with back-gate bias were investigated. Negative back gate bias could raise the influence of buried oxide defects and then degrade the device quickly. For TGFETs with ultra-narrow fin width and side gate extension, the smaller buried oxide interface area and more obvious screening effect terminate the field lines to obviate the back gate bias efficiently. The extrapolated hot-carrier lifetime encourages the TGFETs as promising sub-10nm devices.
UR - http://www.scopus.com/inward/record.url?scp=34250323111&partnerID=8YFLogxK
U2 - 10.1109/VTSA.2006.251076
DO - 10.1109/VTSA.2006.251076
M3 - Conference contribution
AN - SCOPUS:34250323111
SN - 142440181X
SN - 9781424401819
T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
SP - 82
EP - 83
BT - 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
T2 - 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
Y2 - 24 April 2006 through 26 April 2006
ER -