IMITATOR: A deterministic multicore replay system with refining techniques

Shing Yu Chen*, Chi Neng Wen, Geng Hau Yang, Wen Ben Jone, Tien-Fu Chen

*此作品的通信作者

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

Developing parallel programs imposes many debugging challenges on multicore systems. Many researchers were successful to detect parallel faults in background by hardware assistance. However, it is still an urgent issue to reproduce the same faulted circumstance after faults occurred. Tracing the causality between events is a popular solution in current multicore systems, but it is limited by onchip storage and tracing bandwidth. As a result, an intelligent record and replay system is the key to the future multicore debugging problems. This paper proposes IMITATOR for both trace compression and deterministic replay. In contrast to the most other record and replay systems, IMITATOR presents an additional phase, refining phase, between record and replay phases to significantly reduce the recorder overhead, while enabling faster replaying. Results with SPLASH2 benchmark on a 32-core system show that IMITATOR can (a) significantly reduce trace size by the trace refining techniques (16% of native trace) and (b) achieve replay speed 1.96 times faster than the replayer using Sigrace scheme on average.

原文English
主出版物標題2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
出版狀態Published - 2012
事件2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, 台灣
持續時間: 23 4月 201225 4月 2012

出版系列

名字2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
國家/地區台灣
城市Hsinchu
期間23/04/1225/04/12

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