A self-organization algorithm for image compression and the associated VLSI architecture are presented. A frequency upper-threshold is effectively used in the centroid learning method. Performances of the self-organization networks and traditional nonself-organization algorithms for vector quantization are compared. This new algorithm is quite efficient and can achieve near-optimal results. A trainable VLSI neuroprocessor based upon this new self-organization network has been developed for high-speed and high-ratio image compression applications. This neural-based vector quantization design includes a fully parallel vector quantizer and a pipelined codebook generator which obtains a time complexity O (1) for each quantization vector. A 5 × 5-dimensional vector quantizer prototype chip has been designed and fabricated. It contains 64 inner-product neural units and an extendable winner-take-all block. This mixed-signal chip occupies a compact silicon area of 4.6 × 6.8 mm2 in a 2.0-μm scalable CMOS technology. It provides a computing capability as high as 3.33 billion connections per second. It can achieve a speedup factor of 110 compared with a SUN-4/75 workstation for a compression ratio of 33. Real-time adaptive VQ on industrial 1024 × 1024 pixel images is feasible using multiple neuroprocessor chips. An industrial-level design to achieve 104 billion connections per second for the 1024-codevector vector quantizer can be fabricated in a 125 mm2 chip through a 1 μm CMOS technology.