IC design of a high speed RSA processor

Ching Chao Yang*, Chein Wei Jen, Tian-Sheuan Chang

*此作品的通信作者

研究成果: Paper同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this paper, we proposed a new algorithm based on Montgomery's algorithm[1] to calculate modular multiplication that is the core arithmetic operation in RSA cryptosystem. Since the critical path delay in modular multiplication operation is reduced, the new design yields a very fast implementation. We have implemented a 512-bit single chip RSA processor based on our modified algorithm with Compass 0.6μm SPDM cell library. By our modified modular exponentiation algorithm, it takes about 1.5n2 clock cycles to finish one n-bit RSA modular exponentiation operation in our architecture. The simulation results show that we can operate up to 125Mhz, therefore the baud rate of our 512-bit RSA processor is about 164k bits/sec.

原文English
頁面33-36
頁數4
DOIs
出版狀態Published - 1 十二月 1996
事件Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea
持續時間: 18 十一月 199621 十一月 1996

Conference

ConferenceProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems
城市Seoul, South Korea
期間18/11/9621/11/96

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