IAIM: An intelligent autonomous instruction memory with branch handling capability

Hui Chin Yang*, Li Ming Wang, Chung-Ping Chung

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

Goals of this research are to reduce 1. Instruction address bus traffic, 2. Bus power, and 3. Latency, in instructio fetches in a computer system. We propose to move dynamic branch handler from the CPU side to the instruction memory side, and let it be able to autonomously access instructions for CPU. CPU needs only to manage the branch handler. Key to success is that the traffic between CPU and dynamic branch handler, with only minor but innovative design changes, can be far less than that between CPU and instruction memory. The branch handler should hence be capable of PC+4, identifying branches, and target address calculation. We further suggest that even a return stack can easily be incorporated. Simulation using MiBench shows that our theory yields promising results: about 99.98% instruction address traffic and 91.87% related bus bit toggles are reduced.

原文English
主出版物標題Proceedings of the 9th International Conference for Young Computer Scientists, ICYCS 2008
頁面1309-1313
頁數5
DOIs
出版狀態Published - 2008
事件9th International Conference for Young Computer Scientists, ICYCS 2008 - Zhang Jia Jie, Hunan, China
持續時間: 18 11月 200821 11月 2008

出版系列

名字Proceedings of the 9th International Conference for Young Computer Scientists, ICYCS 2008

Conference

Conference9th International Conference for Young Computer Scientists, ICYCS 2008
國家/地區China
城市Zhang Jia Jie, Hunan
期間18/11/0821/11/08

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