Hybrid testbench acceleration for reducing communication overhead

Chin Lung Chuang; Chien-Nan Liu

doi:10.1109/MDT.2011.33

Hybrid testbench acceleration for reducing communication overhead

Chin Lung Chuang, Chien-Nan Liu^*

^*此作品的通信作者

電子研究所

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and software. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator and with only 0.57 hardware overhead.

原文	English
文章編號	5739840
頁（從 - 到）	40-50
頁數	11
期刊	IEEE Design and Test of Computers
卷	28
發行號	2
DOIs	https://doi.org/10.1109/MDT.2011.33
出版狀態	Published - 1 3月 2011

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10.1109/MDT.2011.33

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Hybrid testbench acceleration for reducing communication overhead

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