Hybrid Dry-Wet Chemical Etching Process for Via-Holes for Gallium Arsenide MMIC Manufacturing

Edward Yi Chang, Rao M. Nagarajan, Charles J. Kryzak, Krishna P. Pande

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

Through the wafer via-hole connections for monolithic microwave integrated circuits (MMIC) manufacturing have been developed by combining reactive ion etching (RIE) and wet chemical spray etching processes for 100-μm-thick gallium arsenide wafers. The dry process is based on the use of SiCl4-BCl3-Cl2 and BCl3-Cl2 gas mixtures at room temperature in a reactive ion etcher. The etching parameters are optimized for anisotropic etching, initially, followed by slightly isotropic etching. To remove the residual “lip” and surface roughness, following reactive ion etching, a dynamic wet chemical spray etching based on H3PO4-H2O2-H2O at 45°C is used. The combined dry-wet etching approach is used to fabricate <120-μm diameter via-holes in 100-μm-thick GaAs substrates with a wider process latitude. With this process, we have achieved =95 percent yield across 3-in wafers. Metallized via-hole contacts to power FET chips show a contact resistance <20 mΩ per via for 5-μm-thick selective gold plating.

原文English
頁(從 - 到)157-159
頁數3
期刊IEEE Transactions on Semiconductor Manufacturing
1
發行號4
DOIs
出版狀態Published - 1 一月 1988

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