Hybrid approach to faster functional verification with full visibility

Logic simulators are still the most popular verification tools, and they can provide full controllability and visibility during the verification process. However, their simulation speed is too slow for a large amount of input patterns. Higher speeds are possible with hardware emulation such as FPGAs. But, because of poor visibility in the FPGAs, it is very hard to debug using this approach. The work described in this article focuses on building similar debugging capabilities for low-cost FPGAs that currently are available only in expensive emulators, such as the full visibility provided by software simulators. The authors propose an efficient approach to record an FPGA's internal behavior and replay the interesting period of time in a software simulator. High simulation speed is still possible with this approach because most simulation efforts are completed in the FPGA. Besides this, full visibility and a better debugging environment can be provided in the software simulation while replaying the time frames with errors. To reduce hardware overhead, the authors also propose an algorithm to minimize the amount of recorded data. Experimental results confirm the efficiency of using this approach.