TY - JOUR
T1 - How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on
AU - Ker, Ming-Dou
AU - Chang, Hun Hsien
PY - 1998/12/1
Y1 - 1998/12/1
N2 - In this paper, the lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered on by noise pulses when the IC's are in the normal operating condition. A cascode design is therefore proposed to safely apply the LVTSCR devices for whole-chip ESD protection in CMOS IC's without causing unexpected operation errors or latchup danger. Such cascoded LVTSCR's with a holding voltage greater than VDD of an IC can provide CMOS IC's with effective component-level ESD protection but without being accidentally triggered on by system-level overshooting or undershooting noise pulses.
AB - In this paper, the lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered on by noise pulses when the IC's are in the normal operating condition. A cascode design is therefore proposed to safely apply the LVTSCR devices for whole-chip ESD protection in CMOS IC's without causing unexpected operation errors or latchup danger. Such cascoded LVTSCR's with a holding voltage greater than VDD of an IC can provide CMOS IC's with effective component-level ESD protection but without being accidentally triggered on by system-level overshooting or undershooting noise pulses.
UR - http://www.scopus.com/inward/record.url?scp=0032309711&partnerID=8YFLogxK
U2 - 10.1109/EOSESD.1998.737024
DO - 10.1109/EOSESD.1998.737024
M3 - Conference article
AN - SCOPUS:0032309711
SN - 0739-5159
SP - 72
EP - 85
JO - Electrical Overstress/Electrostatic Discharge Symposium Proceedings
JF - Electrical Overstress/Electrostatic Discharge Symposium Proceedings
T2 - Proceedings of the 1998 20th Annual International EOS/ESD Symposium
Y2 - 6 October 1998 through 8 October 1998
ER -