High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric

Bing Yue Tsui*, Chia Lung Hung, Ya Ru Jhuang, Yi Ting Huang, Jung Chien Cheng, Fang Hsin Lu, Yi Ting Shih, Ya Hsin Lee, Liang Yu Chen, Fu Hsiang Chuang, Pei Wen Li

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

We report a high performance 4H-SiC CMOS process for sub-10 V operation featuring LOCal Oxidation of SiC isolation and balanced gate oxidation process. Temperature stability of SiC MOSFETs and CMOS inverters are characterized up to 300 °C. High voltage gain of 62 V/V and 13 V/V at room temperature and 300 °C, respectively, are demonstrated. The proposed process technology is promising for SiC power system-on-a-chip.

原文English
主出版物標題VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665419345
DOIs
出版狀態Published - 19 4月 2021
事件2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021 - Hsinchu, Taiwan
持續時間: 19 4月 202122 4月 2021

出版系列

名字VLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings

Conference

Conference2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021
國家/地區Taiwan
城市Hsinchu
期間19/04/2122/04/21

指紋

深入研究「High voltage gain 4H-SIC CMOS technology featuring LOCal oxidation of SiC (LOCOSiC) isolation and balanced gate dielectric」主題。共同形成了獨特的指紋。

引用此