High-speed power-efficient coarse-grained convolver architecture using depth-first compression scheme

Yi Lin Wu, Yi Lu, Juinn Dar Huang

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

Convolutional neural networks (CNNs) have been playing an important role in various applications, e.g., computer vision. Since CNN computations require numerous multiply-accumulate (MAC) operations, how to get them done efficiently is a crucial issue for CNN hardware accelerators. In this paper, we propose a high-speed power-efficient convolver architecture for CNN acceleration. A 3×3 convolver is asked to produce an output every cycle and is commonly accomplished by summing up the results of nine parallel multiplications, which requires ten carry-propagation adders (CPAs) in total. However, the proposed coarse-grained convolver can break the boundary between multipliers and reduce all partial products in a more global way. Consequently, it requires only one CPA to generate the final outcome. It also features a globally delay-optimized partial product reduction tree and a depth-first compression scheme for both area and power minimization. The proposed convolver has been implemented using TSMC 40nm technology. Compared to a conventional 3×3 convolver baseline design, our design can reduce area and power by 15.8% and 26.5% respectively at the clock rate of 1GHz.

原文English
主出版物標題2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728133201
DOIs
出版狀態Published - 10月 2020
事件52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online
持續時間: 10 10月 202021 10月 2020

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2020-October
ISSN(列印)0271-4310

Conference

Conference52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
城市Virtual, Online
期間10/10/2021/10/20

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