High-speed digital comb filter for ΣΔ analog-to-digital conversion

Louis Luh*, John Choma, Jeffrey Draper, Her-Ming Chiueh

*此作品的通信作者

研究成果: Paper同行評審

5 引文 斯高帕斯(Scopus)

摘要

A new approach for implementing a digital decimator for high-speed ΣΔ modulators is presented. With the use of carry-saved adders, this decimator is able to operate at high speeds while maintaining the same throughput. By using systematic modular design, this filter can be easily designed and implemented with any order and any length, which greatly reduces the time and effort for circuit design. A prototype of a fourth-order length-16 digital comb filter has been implemented with a 1.2μm standard CMOS process. With a single 5V power supply, this filter can operate at a frequency up to 115MHz. The power consumption is about 35mW and the active area is 1083 × 965 μm2.

原文English
頁面356-359
頁數4
出版狀態Published - 1 12月 1999
事件1999 IEEE 42nd Midwest Symposium on Circuits and Sistems - Las Cruces, NM, USA
持續時間: 8 8月 199911 8月 1999

Conference

Conference1999 IEEE 42nd Midwest Symposium on Circuits and Sistems
城市Las Cruces, NM, USA
期間8/08/9911/08/99

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