High-speed data-plane packet aggregation and disaggregation by P4 switches

Shie-Yuan Wang*, Chia Ming Wu, Yi-Bing Lin, Ching-Chun Huang

*此作品的通信作者

研究成果: Article同行評審

13 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose novel approaches that utilize the header manipulations of the P4 (Programming Protocol-Independent Packet Processor) switches to aggregate small IoT packets into a large one, transmit it over a network, and then disaggregate it back to the original small packets, all in the data plane of the hardware P4 switch to provide high throughputs. Packet aggregation and disaggregation provide many important benefits and have been proposed and performed in the past. However, most existing approaches perform packet aggregation and disaggregation in the control plane either by the switch CPU or by the server CPU, resulting in low throughputs. Our work is the first work that designs and implements packet aggregation and disaggregation purely in the pipelines of the switching ASIC. In this paper, we present the design and implementation of our approaches, their measured throughputs, and the insights that we have obtained from this pioneering work.

原文English
頁(從 - 到)98-110
頁數13
期刊Journal of Network and Computer Applications
142
DOIs
出版狀態Published - 15 9月 2019

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