High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

Tai Hsiang Lai*, Ming-Dou Ker, Wei Jen Chang, Tien Hao Tang, Kuan Cheng Su

*此作品的通信作者

    研究成果: Conference contribution同行評審

    8 引文 斯高帕斯(Scopus)

    摘要

    The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.

    原文English
    主出版物標題46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS
    頁面627-628
    頁數2
    DOIs
    出版狀態Published - 17 9月 2008
    事件46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS - Phoenix, AZ, United States
    持續時間: 27 4月 20081 5月 2008

    出版系列

    名字IEEE International Reliability Physics Symposium Proceedings
    ISSN(列印)1541-7026

    Conference

    Conference46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS
    國家/地區United States
    城市Phoenix, AZ
    期間27/04/081/05/08

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