High-reliability dynamic-threshold source-side injection for 2-bit/cell with MLC operation of wrapped select-gate SONOS in NOR-type flash memory

Kuan Ti Wang; Tien-Sheng Chao; Woei Cherng Wu; Wen Luh Yang; Chien Hsing Lee; Tsung Min Hsieh; Jhyy Cheng Liou; Shen De Wang; Tzu Ping Chen; Chien Hung Chen; Chih Hung Lin; Hwi Huang Chen

doi:10.1109/TED.2010.2054530

High-reliability dynamic-threshold source-side injection for 2-bit/cell with MLC operation of wrapped select-gate SONOS in NOR-type flash memory

Kuan Ti Wang^*, Tien-Sheng Chao, Woei Cherng Wu, Wen Luh Yang, Chien Hsing Lee, Tsung Min Hsieh, Jhyy Cheng Liou, Shen De Wang, Tzu Ping Chen, Chien Hung Chen, Chih Hung Lin, Hwi Huang Chen

^*此作品的通信作者

電子物理學系

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

For the first time, a high-performance Τ_PGM = 200 ns/ΤERS = 5 ms) cell with superior reliability characteristics is demonstrated in a nor-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate siliconoxidenitrideoxidesilicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight V_TH distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.

原文	English
文章編號	5510121
頁（從 - 到）	2335-2338
頁數	4
期刊	IEEE Transactions on Electron Devices
卷	57
發行號	9
DOIs	https://doi.org/10.1109/TED.2010.2054530
出版狀態	Published - 1 9月 2010

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10.1109/TED.2010.2054530

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Wang, K. T., Chao, T-S., Wu, W. C., Yang, W. L., Lee, C. H., Hsieh, T. M., Liou, J. C., Wang, S. D., Chen, T. P., Chen, C. H., Lin, C. H., & Chen, H. H. (2010). High-reliability dynamic-threshold source-side injection for 2-bit/cell with MLC operation of wrapped select-gate SONOS in NOR-type flash memory. IEEE Transactions on Electron Devices, 57(9), 2335-2338. [5510121]. https://doi.org/10.1109/TED.2010.2054530

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title = "High-reliability dynamic-threshold source-side injection for 2-bit/cell with MLC operation of wrapped select-gate SONOS in NOR-type flash memory",

abstract = "For the first time, a high-performance ΤPGM = 200 ns/ΤERS = 5 ms) cell with superior reliability characteristics is demonstrated in a nor-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate siliconoxidenitrideoxidesilicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight VTH distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.",

keywords = "Flash memory, multilevel states in a cell (MLC), NOR, silicon-oxide-nitride- oxide-silicon (SONOS)",

author = "Wang, {Kuan Ti} and Tien-Sheng Chao and Wu, {Woei Cherng} and Yang, {Wen Luh} and Lee, {Chien Hsing} and Hsieh, {Tsung Min} and Liou, {Jhyy Cheng} and Wang, {Shen De} and Chen, {Tzu Ping} and Chen, {Chien Hung} and Lin, {Chih Hung} and Chen, {Hwi Huang}",

year = "2010",

month = sep,

day = "1",

doi = "10.1109/TED.2010.2054530",

language = "English",

volume = "57",

pages = "2335--2338",

journal = "Ieee Transactions On Electron Devices",

issn = "0018-9383",

publisher = "IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",

number = "9",

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Wang, KT, Chao, T-S, Wu, WC, Yang, WL, Lee, CH, Hsieh, TM, Liou, JC, Wang, SD, Chen, TP, Chen, CH, Lin, CH & Chen, HH 2010, 'High-reliability dynamic-threshold source-side injection for 2-bit/cell with MLC operation of wrapped select-gate SONOS in NOR-type flash memory', IEEE Transactions on Electron Devices, 卷 57, 編號 9, 5510121, 頁 2335-2338. https://doi.org/10.1109/TED.2010.2054530

TY - JOUR

T1 - High-reliability dynamic-threshold source-side injection for 2-bit/cell with MLC operation of wrapped select-gate SONOS in NOR-type flash memory

AU - Wang, Kuan Ti

AU - Chao, Tien-Sheng

AU - Wu, Woei Cherng

AU - Yang, Wen Luh

AU - Lee, Chien Hsing

AU - Hsieh, Tsung Min

AU - Liou, Jhyy Cheng

AU - Wang, Shen De

AU - Chen, Tzu Ping

AU - Chen, Chien Hung

AU - Lin, Chih Hung

AU - Chen, Hwi Huang

PY - 2010/9/1

Y1 - 2010/9/1

N2 - For the first time, a high-performance ΤPGM = 200 ns/ΤERS = 5 ms) cell with superior reliability characteristics is demonstrated in a nor-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate siliconoxidenitrideoxidesilicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight VTH distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.

AB - For the first time, a high-performance ΤPGM = 200 ns/ΤERS = 5 ms) cell with superior reliability characteristics is demonstrated in a nor-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate siliconoxidenitrideoxidesilicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight VTH distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.

KW - Flash memory

KW - multilevel states in a cell (MLC)

KW - NOR

KW - silicon-oxide-nitride- oxide-silicon (SONOS)

UR - http://www.scopus.com/inward/record.url?scp=77956063175&partnerID=8YFLogxK

U2 - 10.1109/TED.2010.2054530

DO - 10.1109/TED.2010.2054530

M3 - Article

AN - SCOPUS:77956063175

SN - 0018-9383

VL - 57

SP - 2335

EP - 2338

JO - Ieee Transactions On Electron Devices

JF - Ieee Transactions On Electron Devices

IS - 9

M1 - 5510121

ER -

High-reliability dynamic-threshold source-side injection for 2-bit/cell with MLC operation of wrapped select-gate SONOS in NOR-type flash memory

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