High performance silicon N-channel gate-all-around junctionless field effect transistors by strain technology

P. J. Sung, T. C. Cho, P. C. Chen, F. J. Hou, C. H. Lai, Y. J. Lee, Yi-Ming Li, S. Samukawa, Tien-Sheng Chao, W. F. Wu, W. K. Yeh

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

In this paper, strain effects on silicon n-channel gate-all-around (GAA) jucntionless field effect transistor (JLFET) are studied. By using tensile strain SiN layer, drive currents of the JLFETs show enhancement of up to 42%. The high performance strained JLFETs exhibit superior gate control (Ion/Ioff >109) and ideal S.S. (65 mV/dec.) as a channel width scales down to 20 nm. Drive currents and leakage currents are improved simultaneously after inducing strain technology.

原文English
主出版物標題16th International Conference on Nanotechnology - IEEE NANO 2016
發行者Institute of Electrical and Electronics Engineers Inc.
頁面174-175
頁數2
ISBN(電子)9781509039142
DOIs
出版狀態Published - 21 11月 2016
事件16th IEEE International Conference on Nanotechnology - IEEE NANO 2016 - Sendai, Japan
持續時間: 22 8月 201625 8月 2016

出版系列

名字16th International Conference on Nanotechnology - IEEE NANO 2016

Conference

Conference16th IEEE International Conference on Nanotechnology - IEEE NANO 2016
國家/地區Japan
城市Sendai
期間22/08/1625/08/16

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