High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

Dong Ru Hsieh, Jer Yi Lin, Po Yi Kuo, Tien-Sheng Chao*

*此作品的通信作者

研究成果: Article同行評審

14 引文 斯高帕斯(Scopus)

摘要

In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width ∼ 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si3N4) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG poly-Si JL FETs show excellent electrical performance in terms of low gate overdrive voltage (VG - VTH = 2 V), extremely near-ideal subthreshold swing (S.S.) ∼68 mV/decade, steep average subthreshold swing (A.S.S.) ∼73 mV/decade, smaller drain-induced barrier lowering ∼9 mV/V, a higher ON/OFF current ratio ∼1.1 × 108 (VD = 1 V), and a better field-effect mobility (μFE) ∼ 35 (cm2/Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications.

原文English
文章編號7582399
頁(從 - 到)4179-4184
頁數6
期刊IEEE Transactions on Electron Devices
63
發行號11
DOIs
出版狀態Published - 11月 2016

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