High-performance NAND flash controller exploiting parallel out-of-order command execution

Yu Hsiang Kao*, Juinn-Dar Huang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    7 引文 斯高帕斯(Scopus)

    摘要

    NAND flash memory is one of the most important components in modern non-volatile storage media. However, long command setup time and slow I/O interface frequency of current NAND flash device has been limiting the bandwidth of data transfer. In this paper, we propose a high-performance NAND flash controller architecture by exploiting two techniques - parallel out-of-order execution of multi-die commands and two-plane address translation. By these two techniques, the number of commands being executed in parallel can be maximized and the average execution time per command can thus be greatly reduced to achieve higher performance. The experimental results show that the proposed NAND flash controller can improve the data access performance in both read and program for at least 18% as compared to a baseline NAND flash controller.

    原文English
    主出版物標題Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
    頁面160-163
    頁數4
    DOIs
    出版狀態Published - 2010
    事件2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, 台灣
    持續時間: 26 4月 201029 4月 2010

    出版系列

    名字Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

    Conference

    Conference2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
    國家/地區台灣
    城市Hsin Chu
    期間26/04/1029/04/10

    指紋

    深入研究「High-performance NAND flash controller exploiting parallel out-of-order command execution」主題。共同形成了獨特的指紋。

    引用此