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High-performance GAA sidewall-damascened sub-10-nm in situ n
+
-doped poly-Si NWs channels junctionless FETs
Po Yi Kuo
*
, Yi Hsien Lu
,
Tien-Sheng Chao
*
此作品的通信作者
電子物理學系
研究成果
:
Article
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同行評審
26
引文 斯高帕斯(Scopus)
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深入研究「High-performance GAA sidewall-damascened sub-10-nm in situ n
+
-doped poly-Si NWs channels junctionless FETs」主題。共同形成了獨特的指紋。
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Keyphrases
In Situ
100%
Poly-Si
100%
High Performance
100%
Silicon Nanowires (SiNWs)
100%
Sidewall
100%
Sub-10 Nm
100%
Junctionless FET
100%
Electrical Characteristics
40%
On-chip Applications
20%
Thermal Stability
20%
Cross-sectional Area
20%
Supply Voltage
20%
3D IC
20%
Transistor
20%
ION-IOFF
20%
High Thermal Stability
20%
Subthreshold Swing
20%
Poly-Si Nanowire
20%
Threshold Voltage
20%
System on Panel
20%
Plasma Treatment
20%
Gate-all-around
20%
Nanowire Channel
20%
On-off Ratio
20%
Steep Subthreshold Swing
20%
High Temperature Operation
20%
Integrated Circuit System
20%
Physics
Integrated Circuit
100%
Threshold Voltage
100%
Operating Temperature
100%
Blood Plasma
100%
Nanowire
100%
Engineering
Field Effect Transistor
100%
Side Wall
100%
Polysilicon
100%
Supply Voltage
25%
System-on-Chip
25%
Plasma Treatment
25%
Current Ratio
25%
Si Nanowires
25%
High Operating Temperature
25%
Integrated Circuit
25%
Chemical Engineering
Polysilicon
100%
Nanowire
25%