High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

Y. J. Lee, T. C. Hong, F. K. Hsueh, P. J. Sung, C. Y. Chen, S. S. Chuang, T. C. Cho, S. Noda, Y. C. Tsou, K. H. Kao, C. T. Wu, T. Y. Yu, Y. L. Jian, C. J. Su, Y. M. Huang, W. H. Huang, B. Y. Chen, M. C. Chen, K. P. Huang, J. Y. LiM. J. Chen, Yi-Ming Li, S. Samukawa, W. F. Wu, G. W. Huang, J. M. Shieh, Tseung-Yuen Tseng, Tien-Sheng Chao, Y. H. Wang, W. K. Yeh

研究成果: Conference contribution同行評審

9 引文 斯高帕斯(Scopus)

摘要

Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) Ion and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high Ion/Ioff ratio and low subthreshold swing (S.S. ∼ 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.

原文English
主出版物標題2016 IEEE International Electron Devices Meeting, IEDM 2016
發行者Institute of Electrical and Electronics Engineers Inc.
頁面33.5.1-33.5.4
ISBN(電子)9781509039012
DOIs
出版狀態Published - 31 1月 2017
事件62nd IEEE International Electron Devices Meeting, IEDM 2016 - San Francisco, United States
持續時間: 3 12月 20167 12月 2016

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
ISSN(列印)0163-1918

Conference

Conference62nd IEEE International Electron Devices Meeting, IEDM 2016
國家/地區United States
城市San Francisco
期間3/12/167/12/16

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