High-frequency characteristics of PMOS transistors with raised SiGe source/drain

As the performance of small geometry CMOS improves, sub-0.1 μm Si MOSFETs have good RF characteristics, and are expected to replace bipolar and GaAs MESFETs in RF front-end ICs in the near future. However, the parasitic components will be a limiting factor as the device is scaled down to the sub-0.1 μm region. In this work, we report a p-channel MOSFET with raised Si _1-x Ge _x source/drain (S/D) structure to reduce the parasitic resistance. We find that the selective epitaxial layer can effectively reduce the gate and S/D sheet resistances. In addition, due to the lower Schottky barrier height of the metal/p-Si _1-x Ge _x junction, low S/D contact resistivity can be achieved. For gate length L _g =0.5 μm, Si _0.86 Ge _0.14 PMOS exhibits roughly 12% f _T improvement over the conventional Si PMOS. Moreover, the device with raised Si _0.86 Ge _0.14 S/D structure produces a 27% improvement in f _T at a gate length of 0.2 μm. This illustrates the importance of maintaining a low series resistance as devices are scaled down.