High endurance multi-gate TiN nanocrystal memory devices with high-k blocking dielectric and high work function gate electrode

C. P. Lu, C. K. Luo, Bing-Yue Tsui, C. H. Lin, P. J. Tzeng, C. C. Wang, H. Y. Lee, D. Y. Wu, M. J. Tsai

    研究成果: Conference contribution同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    In this work, n-channel Multi-gate FET TiN nanocrystal memory using p + poly-Si gate and Al2O3 high-k blocking dielectric is demonstrated with good transistor characteristics and moderate high memory window for the first time. High endurance of only 3% window narrowing after 104 P/E cycles is demonstrated. The phenomenon and mechanism of erasing-first induced retention degradation are also reported.

    原文English
    主出版物標題2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
    頁面62-63
    頁數2
    DOIs
    出版狀態Published - 2008
    事件2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Hsinchu, Taiwan
    持續時間: 21 4月 200823 4月 2008

    出版系列

    名字International Symposium on VLSI Technology, Systems, and Applications, Proceedings

    Conference

    Conference2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
    國家/地區Taiwan
    城市Hsinchu
    期間21/04/0823/04/08

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