High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

Wen Quan He; Yuan Ho Chen; Shyh-Jye Jou

doi:10.1109/TCSI.2015.2440731

High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

Wen Quan He, Yuan Ho Chen, Shyh-Jye Jou

研究成果: Article › 同行評審

17 引文斯高帕斯（Scopus）

摘要

This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-μm CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.

原文	English
文章編號	7166389
頁（從 - 到）	2052-2061
頁數	10
期刊	IEEE Transactions on Circuits and Systems I: Regular Papers
卷	62
發行號	8
DOIs	https://doi.org/10.1109/TCSI.2015.2440731
出版狀態	Published - 1 8月 2015

存取文件

10.1109/TCSI.2015.2440731

其它文件與鏈接

Link to publication in Scopus

引用此

@article{4c042b83d85a43409e71f67b6613bc50,

title = "High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation",

abstract = "This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-μm CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.",

keywords = "Booth encoder, dynamic error-compensation, fixed-width multiplier, mathematical probable model",

author = "He, {Wen Quan} and Chen, {Yuan Ho} and Shyh-Jye Jou",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.",

year = "2015",

month = aug,

day = "1",

doi = "10.1109/TCSI.2015.2440731",

language = "English",

volume = "62",

pages = "2052--2061",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-8328",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "8",

}

TY - JOUR

T1 - High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

AU - He, Wen Quan

AU - Chen, Yuan Ho

AU - Jou, Shyh-Jye

PY - 2015/8/1

Y1 - 2015/8/1

N2 - This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-μm CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.

AB - This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-μm CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.

KW - Booth encoder

KW - dynamic error-compensation

KW - fixed-width multiplier

KW - mathematical probable model

UR - http://www.scopus.com/inward/record.url?scp=84938400309&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2015.2440731

DO - 10.1109/TCSI.2015.2440731

M3 - Article

AN - SCOPUS:84938400309

SN - 1549-8328

VL - 62

SP - 2052

EP - 2061

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 8

M1 - 7166389

ER -

High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

摘要

存取文件

其它文件與鏈接

指紋

引用此