High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

Wen Quan He, Yuan Ho Chen, Shyh-Jye Jou

    研究成果: Article同行評審

    14 引文 斯高帕斯(Scopus)

    摘要

    This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-μm CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.

    原文English
    文章編號7166389
    頁(從 - 到)2052-2061
    頁數10
    期刊IEEE Transactions on Circuits and Systems I: Regular Papers
    62
    發行號8
    DOIs
    出版狀態Published - 1 8月 2015

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