High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory

Yun Yan Chung, Chao Ching Cheng, Yu Che Chou, Wei Chen Chueh, Wan Hsuan Chung, Zhihao Yu, Terry Yi Tse Hung, Lin Yun Huang, Shin Yuan Wang, Li Cheng Teng, Wen Ho Chang, Lain Jong Li, Chao Hsin Chien*

*此作品的通信作者

    研究成果: Article同行評審

    摘要

    The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( text{R}{text {ON}} ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max-min ratio ( {G}{text {MAX}}/ ∼{G}{text {MIN}} ; 50), low nonlinearity of alpha{text {p}} = -0.81 and alpha{text {d}} = -0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained.

    原文English
    文章編號9206053
    頁(從 - 到)1649-1652
    頁數4
    期刊Ieee Electron Device Letters
    41
    發行號11
    DOIs
    出版狀態Published - 十一月 2020

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