Hierarchical techniques for symbolic analysis of large electronic circuits

Shyh-Jye Jou; Mei Fang Perng; Chau-Chin Su; C. K. Wang

doi:10.1109/ISCAS.1994.408745

Hierarchical techniques for symbolic analysis of large electronic circuits

Shyh-Jye Jou^*, Mei Fang Perng, Chau-Chin Su, C. K. Wang

^*此作品的通信作者

研究成果: Conference article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A hierarchical symbolic analyzer(SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.

原文	English
頁（從 - 到）	21-24
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	1
DOIs	https://doi.org/10.1109/ISCAS.1994.408745
出版狀態	Published - 1 12月 1994
事件	Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England 持續時間: 30 5月 1994 → 2 6月 1994

存取文件

10.1109/ISCAS.1994.408745

其它文件與鏈接

Link to publication in Scopus

引用此

@article{e6ea45f26f8d41909a27b325ab953f17,

title = "Hierarchical techniques for symbolic analysis of large electronic circuits",

abstract = "A hierarchical symbolic analyzer(SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.",

author = "Shyh-Jye Jou and Perng, {Mei Fang} and Chau-Chin Su and Wang, {C. K.}",

year = "1994",

month = dec,

day = "1",

doi = "10.1109/ISCAS.1994.408745",

language = "English",

volume = "1",

pages = "21--24",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 30-05-1994 Through 02-06-1994",

}

TY - JOUR

T1 - Hierarchical techniques for symbolic analysis of large electronic circuits

AU - Jou, Shyh-Jye

AU - Perng, Mei Fang

AU - Su, Chau-Chin

AU - Wang, C. K.

PY - 1994/12/1

Y1 - 1994/12/1

N2 - A hierarchical symbolic analyzer(SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.

AB - A hierarchical symbolic analyzer(SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.

UR - http://www.scopus.com/inward/record.url?scp=0028554088&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.1994.408745

DO - 10.1109/ISCAS.1994.408745

M3 - Conference article

AN - SCOPUS:0028554088

SN - 0271-4310

VL - 1

SP - 21

EP - 24

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

Y2 - 30 May 1994 through 2 June 1994

ER -

Hierarchical techniques for symbolic analysis of large electronic circuits

摘要

存取文件

其它文件與鏈接

指紋

引用此