Hierarchical techniques for symbolic analysis of electronic circuits

Shyh-Jye Jou; M. F. Perng; Chau-Chin Su

doi:10.1049/ip-cds:19970871

Hierarchical techniques for symbolic analysis of electronic circuits

Shyh-Jye Jou^*
, M. F. Perng
, Chau-Chin Su

^*此作品的通信作者

研究成果: Article › 同行評審

摘要

A hierarchical symbolic analyser (SAGA2) is presented for the analysis of electronic circuits. SAGA2 analyses lumped, linear, or linearised (small-signal) circuits in the S- and Z-domain. For the analysis of large circuits, a hierarchical two-port (multiport) method is proposed that is two to three orders faster than that without using the hierarchical method. A bandpass filter or a 12-stage RC ladder circuit can be analysed in symbolic form within 1 CPU second. Also, the memory used is dramatically reduced.

原文	English
頁（從 - 到）	167-177
頁數	11
期刊	IEE Proceedings: Circuits, Devices and Systems
卷	144
發行號	3
DOIs	https://doi.org/10.1049/ip-cds:19970871
出版狀態	Published - 1997

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@article{3469d23102b148fd8a8c58412579765f,

title = "Hierarchical techniques for symbolic analysis of electronic circuits",

abstract = "A hierarchical symbolic analyser (SAGA2) is presented for the analysis of electronic circuits. SAGA2 analyses lumped, linear, or linearised (small-signal) circuits in the S- and Z-domain. For the analysis of large circuits, a hierarchical two-port (multiport) method is proposed that is two to three orders faster than that without using the hierarchical method. A bandpass filter or a 12-stage RC ladder circuit can be analysed in symbolic form within 1 CPU second. Also, the memory used is dramatically reduced.",

keywords = "Bandpass filter, Electronic circuit, Rc ladder circuit, Symbolic analyser",

author = "Shyh-Jye Jou and Perng, \{M. F.\} and Chau-Chin Su",

year = "1997",

doi = "10.1049/ip-cds:19970871",

language = "English",

volume = "144",

pages = "167--177",

journal = "IEE Proceedings: Circuits, Devices and Systems",

issn = "1350-2409",

publisher = "Institution of Engineering and Technology",

number = "3",

}

TY - JOUR

T1 - Hierarchical techniques for symbolic analysis of electronic circuits

AU - Jou, Shyh-Jye

AU - Perng, M. F.

AU - Su, Chau-Chin

PY - 1997

Y1 - 1997

N2 - A hierarchical symbolic analyser (SAGA2) is presented for the analysis of electronic circuits. SAGA2 analyses lumped, linear, or linearised (small-signal) circuits in the S- and Z-domain. For the analysis of large circuits, a hierarchical two-port (multiport) method is proposed that is two to three orders faster than that without using the hierarchical method. A bandpass filter or a 12-stage RC ladder circuit can be analysed in symbolic form within 1 CPU second. Also, the memory used is dramatically reduced.

AB - A hierarchical symbolic analyser (SAGA2) is presented for the analysis of electronic circuits. SAGA2 analyses lumped, linear, or linearised (small-signal) circuits in the S- and Z-domain. For the analysis of large circuits, a hierarchical two-port (multiport) method is proposed that is two to three orders faster than that without using the hierarchical method. A bandpass filter or a 12-stage RC ladder circuit can be analysed in symbolic form within 1 CPU second. Also, the memory used is dramatically reduced.

KW - Bandpass filter

KW - Electronic circuit

KW - Rc ladder circuit

KW - Symbolic analyser

UR - https://www.scopus.com/pages/publications/0031170213

U2 - 10.1049/ip-cds:19970871

DO - 10.1049/ip-cds:19970871

M3 - Article

AN - SCOPUS:0031170213

SN - 1350-2409

VL - 144

SP - 167

EP - 177

JO - IEE Proceedings: Circuits, Devices and Systems

JF - IEE Proceedings: Circuits, Devices and Systems

IS - 3

ER -

Hierarchical techniques for symbolic analysis of electronic circuits

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