Hierarchical techniques for symbolic analysis of electronic circuits

Shyh-Jye Jou*, M. F. Perng, Chau-Chin Su

*此作品的通信作者

研究成果: Article同行評審

摘要

A hierarchical symbolic analyser (SAGA2) is presented for the analysis of electronic circuits. SAGA2 analyses lumped, linear, or linearised (small-signal) circuits in the S- and Z-domain. For the analysis of large circuits, a hierarchical two-port (multiport) method is proposed that is two to three orders faster than that without using the hierarchical method. A bandpass filter or a 12-stage RC ladder circuit can be analysed in symbolic form within 1 CPU second. Also, the memory used is dramatically reduced.

原文English
頁(從 - 到)167-177
頁數11
期刊IEE Proceedings: Circuits, Devices and Systems
144
發行號3
DOIs
出版狀態Published - 1 一月 1997

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