摘要
A hierarchical symbolic analyser (SAGA2) is presented for the analysis of electronic circuits. SAGA2 analyses lumped, linear, or linearised (small-signal) circuits in the S- and Z-domain. For the analysis of large circuits, a hierarchical two-port (multiport) method is proposed that is two to three orders faster than that without using the hierarchical method. A bandpass filter or a 12-stage RC ladder circuit can be analysed in symbolic form within 1 CPU second. Also, the memory used is dramatically reduced.
| 原文 | English |
|---|---|
| 頁（從 - 到） | 167-177 |
| 頁數 | 11 |
| 期刊 | IEE Proceedings: Circuits, Devices and Systems |
| 卷 | 144 |
| 發行號 | 3 |
| DOIs | |
| 出版狀態 | Published - 1997 |